Development of integrated circuit packaging technology
The development of IC packaging technology the development of IC packaging technology is accompanied by the development of IC chips, generally speaking, "a generation of chips needs a generation of packaging." The history of encapsulation is also the history of chip performance improvement and system miniaturization. With the reduction of the size of IC devices and the improvement of the running speed, new and higher requirements are put forward for IC.
Review packaging industry development process, we according to the packaging technology process, to the year 2000 as the node, the packaging industry is divided into traditional packaging stage and advanced packaging stage.
The development of traditional packaging technology can be subdivided into three stages. Its characteristics can be summarized as follows: technical: to-DIplCC-QFP-BGA-CSP; Pin shape: long lead straight insert - short lead or leadless mount - spherical convex point welding; Assembly method: through-hole packing-surface installation-direct installation; Bonding mode: lead connection - solder ball connection.
Stage 1 (before 1980) : the era of Through Hole (TH), characterized by jholes installed on PCB, pins less than 64, fixed pitch, maximum installation density of 10 pins /cm2, represented by metal circular package (TO) and double-row in-line package (DIP);
Stage 2 (1980-1990) : Surface Mount (SMT) era, characterized by lead instead of pin, winged or tape-shaped lead, two or four-sided lead, pitch 1.27-0.44mm, suitable for 3-300 leads, installation density 10-50 pins /cm2, represented by small shape package (SOP) and four-sided pin flat package (QFP);
Stage 3 (1990-2000) : In the era of area array packaging, represented by BGA and CSP in single chip technology, "ball welding" was used instead of "pin", and the connection distance between the chip and the system was greatly shortened. In terms of pattern evolution, represented by multi-chip components (MCM), multiple chips can be assembled into various electronic components and subsystems on high-density multi-layer interconnected substrates by surface mount technology.
Since the mid-1990s, the IC sealing and testing industry has entered the era of 3D stacking packaging (3D) due to the continuous demand of multi-functional system products and the introduction of CSP packaging and multilayer substrate technology. The specific characteristics are as follows :(1) the concept of encapsulating element evolves into encapsulating system;
(2) Single chip to multi-chip development; (3) Planar encapsulation (MCM) is developing into three-dimensional encapsulation (3D). (4) Flip connection and TSV silicon through-hole connection become the main bonding methods. Specific advanced packaging includes flip, wafer level packaging, POP/Sip/TSV and other three-dimensional packaging technologies, whose characteristics are described as follows:
3D packaging technology: MCM technology integrates multiple integrated circuit chips to realize the integration of packaging products in area, so the vertical integration of chip integration is the main effect of 3D packaging technology. 3D encapsulation can be achieved in two ways: shrink-wrapped stack and encapsulated stack. Encapsulation stack can be divided into encapsulation stack within encapsulation and encapsulation stack between encapsulation. 3D packaging will comprehensively use inversion, wafer level packaging, POP/Sip/TSV and other three-dimensional packaging technologies, and its development is divided into three stages:
The first stage USES the technology of lead and flip chip bonding to stack the chip.
The second stage adopts encapsulation stack (POP).
The third stage USES silicon through hole technology to realize chip stack.
Flip Chip (FC) is not a specific type of package, but a kind of circuit interconnection technology between tube core and package carrier. It is a more advanced connection technology developed by Wire Bond (WB) and Tape Automated Bonding (TAB). The chip welding plate of WB and TAB is limited to around the chip, while FC makes the bare chip face down to directly connect the whole chip area to the substrate, eliminating the connection lead and providing better electrical performance.
Wafer Level Package (WLP) technology is the product of the combination of flip technology with SMT and BGA in the constant pursuit of miniaturization by the market. It is a kind of CSP that has been improved and improved.
Wafer level packaging and traditional packaging methods (cutting and then testing and packaging area at least > 20% after the original chip area), there is a big difference between WLP technology on the whole wafer first for the numerous chip packaging, testing, and finally cut into a single device, and loaded on the board or PCB directly, so the packaging volume is equal to the chip after the original size, the production cost is greatly reduced. WLP is also known as standard WLP (Fanin WLP), and then evolved into spread WLP (Fanout WLP), which is based on wafer reconstruction technology. The chip is rearranged on an artificial wafer, and then packaged in accordance with the lace steps of standard WLP process.
Stacked Package (Package on Package, PoP) belongs to the outer packaging, refers to the vertical arrangement of logic and storage components of the integrated circuit packaging form, it USES two or more than two stack of BGA, general logic operations at the bottom, under strong resistance to store components located in the upper, combines two encapsulated with solder ball is mainly used in the manufacture of advanced portable devices and smartphones using advanced mobile communication platform.
TSV (Through -Silicon-Via) is also a circuit interconnection technology that interconnects chips by creating vertical conduction between chips and wafers and between wafers. Unlike previous IC encapsulation bonding and convex point stacking techniques, TSV enables chips to stack in 3d with maximum density and minimum dimensions, and greatly improves chip speed and low-power performance. TSV is a key technology for 2.5D and 3D packaging.
System in a Package (SiP) is the integration of a variety of functional chips, including processors, memory and other functional chips in a Package, so as to achieve a basically complete function. Corresponding to System On a Chip (SoC). The difference is that system-level packaging adopts the side-by-side or superimposed packaging mode of different chips, while SOC is a highly integrated chip product.
On the whole, packaging technology has experienced the evolution from traditional packaging (DIP, SOP, QFP, PGA, etc.) to advanced packaging (BGA, CSP, FC, WLP, TSV, 3D stack, SIP, etc.). At present, the world's integrated circuit packaging technology is the third generation of packaging technology, namely BGA (ball grid array packaging), CSP (chip level packaging), FC (flip chip). Flip chip packaging technology is considered as a necessary technology to promote the manufacturing of low-cost, high-density portable electronic equipment, and has been widely used in consumer electronics market. The fourth-generation packaging technologies, such as WLP (wafer level packaging), TSV (silicon through-hole technology) and SIP (system-level packaging), are still in the small scale promotion, and they will also become the mainstream of future packaging methods under the technology upgrade.
The domestic packaging industry took the lead in breaking through
The scale of the global IC test sealing industry has maintained a single-digit growth (except for the sharp increase in 2014, which led to a slight decrease in the data in 2015). In 2017, the global test sealing industry's revenue was 53.3 billion US dollars, accounting for 13% of the overall revenue of the semiconductor industry. In 2018, the global test sealing industry's revenue is expected to be 56 billion US dollars, maintaining a growth rate of 4.5%. According to the regional statistics of the top 25 test manufacturers, Taiwan occupies half of the test industry with 53% sales, followed by Mainland China and the United States, ranking the second and third with 21% and 15% share respectively, while Malaysia, South Korea, Singapore and Japan occupy 4%, 3%, 2% and 2% share respectively
As Moore's Law comes to an end and IC costs continue to rise, the industry has begun to rely on IC packaging to expand its profits beyond Moore's time. Therefore, thanks to the broad demand for higher integration and the promotion of downstream trends such as 5G, consumer, storage and computing, Internet of Things, artificial intelligence and high performance computing, advanced packaging will become the main driving force to promote IC packaging industry. According to Yole's data, advanced packaging and traditional packaging accounted for 42.1% and 57.9% respectively in 2018. Meanwhile, it is predicted that the compound growth rate of the industry as a whole will be 5% by 2024. Among them, advanced packaging will account for 49.7%, in line with the growth rate of 8.2%, accounting for half of the industry's overall share. Traditional packaging maintained a compound growth rate of 2.4 percent, the share of gradually shrinking.
From the perspective of advanced packaging technology platform segmentation, inversion technology is the most widely used, accounting for about 75% of the market share, followed by Fan-in WLP and Fanout WLP. From the perspective of future development speed, Yole predicted that from 2018-2024, 2D/3D TSV technology, Embedded package technology and Fen-out WLP would grow rapidly due to the vast market space in the future, maintaining compound growth rates of 26%, 49% and 26% respectively. Among them, Fanout will be mainly used in the fields of mobile Internet, network and automobile. The 2D/3D TSV technology will be mainly applied in artificial intelligence (AI)/machine learning (ML), high performance computing (HPC), data center, image sensor, and mEMS fields. Embedded Die technology is mainly used in the automotive and medical fields.
Benefiting from the rise of the downstream consumer electronics industry and the trend of semiconductor industry transfer, China's IC sealed test industry has been developing rapidly. Since 2015, it has maintained a double-digit growth trend, far higher than the global growth rate. According to statistics released by The Foresight Industry Research Institute, the market size of China's INTEGRATED circuit packaging and testing industry in 2018 exceeded 200 billion yuan, reaching 219.39 billion yuan, up 16.1 percent year on year.
The proportion of advanced packaging in China is low but growing rapidly. Although in recent years, leading domestic enterprises have made great breakthroughs in the field of advanced packaging, and the industrialization capacity of advanced packaging has basically formed, there is still a certain gap between Chinese packaging enterprises and international advanced level in advanced packaging aspects such as high-density integration. At present, China's IC packaging market is still dominated by DIP, QFP, QFN/DFN and other traditional packaging technologies. According to the statistics of Jibon Consulting, in 2018, China's advanced packaging revenue was about 52.6 billion yuan, accounting for 25% of China's TOTAL IC packaging revenue, far lower than the global 42.1%. Domestic advanced packaging market share is only about 10% of the global market share. Yole data shows that In 2018, Chinese companies accelerated the increase of production capacity in advanced packaging field, with a growth rate of up to 16%, double that of the world. After the acquisition of Xinke Jinpeng, CJTS accounted for 7.8% of its shipments of advanced packaging products in the world (2017), ranking the third, only behind Intel and Spil.
Domestic packaging enterprises have entered the world's first echelon, has a certain degree of international competitiveness. Development of integrated circuit packaging technology
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